МІНІСТЕРСТВО ОСВІТИ І НАУКИ УКРАЇНИ НАЦІОНАЛЬНИЙ УНІВЕРСИТЕТ “ЛЬВІВСЬКА ПОЛІТЕХНІКА”
КУРСОВА РОБОТА VHDL-частина з курсу “Комп’ютерна схемотехніка” на тему: “Запам’ятовувальний пристрій з мікропрограмним керуванням” Львів – 2012 Таблиця істинності ПЗП A Q1 Q0 Y1 Y0 K3 K2 K1 K0 D1 D0 B  0 0 0 0 0 0 0 1 0 1 0 10  1 0 0 0 1 0 1 0 0 0 0 16  2 0 0 1 0 0 1 0 0 1 1 19  3 0 0 1 1 0 0 0 1 0 1 5  4 0 1 0 0 1 1 0 0 0 1 49  5 0 1 0 1 0 1 0 0 1 0 18  6 0 1 1 0 0 0 1 0 1 0 10  7 0 1 1 1 0 1 0 0 1 0 18  8 1 0 0 0 1 1 0 0 1 0 50  9 1 0 0 1 0 0 0 1 0 0 4  10 1 0 1 0 0 0 0 1 1 1 7  11 1 0 1 1 1 1 0 0 1 0 50  12 1 1 0 0 0 0 0 1 0 0 4  13 1 1 0 1 0 1 0 0 0 1 17  14 1 1 1 0 0 0 0 1 1 1 7  15 1 1 1 1 0 1 0 0 1 0 18   8 4 2 1 32 16 8 4 2 1    Схема
VHDL-опис PZP architecture PZP of PZP is type A is array (0 to 15) of STD_LOGIC_VECTOR(5 downto 0); constant Word:A:=("010010" ,"000111" ,"010001" ,"000100" ,"110010" ,"000111" ,"000100" ,"110010" ,"010010" ,"001010" ,"010010" ,"110001" ,"000101" ,"010011" ,"010000" ,"001010"); begin process (Adr3, Adr2, Adr1, Adr0) begin Data<= Word(Conv_Integer(Adr3&Adr2&Adr1&Adr0)); end process; end architecture; VHDL-опис Reg library IEEE ; use IEEE.std_logic_1164.all; use IEEE.std_logic_unsigned.all; entity REG is port( CLK: in std_logic; DataIn: in std_logic_vector(5 downto 0); Res: in std_logic; DataOut5: out std_logic; DataOut4: out std_logic; DataOut3: out std_logic; DataOut2: out std_logic; DataOut1: out std_logic; DataOut0: out std_logic ); end REG; architecture REG of REG is signal Save:std_logic_vector(5 downto 0):=(others => 'Z'); begin D:process (CLK, RES) begin if CLK'event and CLK = '1' then if RES = '0' then Save <= "000000"; DataOut5<= Save(5); DataOut4<= Save(4); DataOut3<= Save(3); DataOut2<= Save(2); DataOut1<= Save(1); DataOut0<= Save(0); else DataOut5<= Save(5); DataOut4<= Save(4); DataOut3<= Save(3); DataOut2<= Save(2); DataOut1<= Save(1); DataOut0<= Save(0); end if; else if RES = '0' then Save <="000000"; DataOut5<= Save(5); DataOut4<= Save(4); DataOut3<= Save(3); DataOut2<= Save(2); DataOut1<= Save(1); DataOut0<= Save(0); else DataOut5<= Save(5); DataOut4<= Save(4); DataOut3<= Save(3); DataOut2<= Save(2); DataOut1<= Save(1); DataOut0<= Save(0); save<=DataIn; end if; end if; end process; end architecture; VHDL-опис NOT library IEEE; use IEEE.std_logic_1164.all; entity NOT1 is port( A:in std_logic; F:out std_logic); end entity; architecture NOT1 of NOT1 is begin F<=not(A); end architecture; VHDL-опис MUX library IEEE; use IEEE.STD_LOGIC_1164.all; entity MUX is port( E : in STD_LOGIC; A0 : in STD_LOGIC; A1 : in STD_LOGIC; A2 : in STD_LOGIC; D0 : in STD_LOGIC; D1 : in STD_LOGIC; D2 : in STD_LOGIC; D3 : in STD_LOGIC; D4 : in STD_LOGIC; D5 : in STD_LOGIC; D6 : in STD_LOGIC; D7 : in STD_LOGIC; OutP : out STD_LOGIC ); end MUX; architecture MUX of MUX is begin process(E, A0, A1, A2) begin if E='0' then if A0='0' and A1='0' and A2='0' then OutP<=D0; elsif A0='0' and A1='0' and A2='1' then OutP<=D1; elsif A0='0' and A1='1' and A2='0' then OutP<=D2; elsif A0='0' and A1='1' and A2='1' then OutP<=D3; elsif A0='1' and A1='0' and A2='0' then OutP<=D4; elsif A0='1' and A1='0' and A2='1' then OutP<=D5; elsif A0='1' and A1='1' and A2='0' then Ou...